Archive for June, 2005

Mulitcore developer info from Intel

Thursday, June 9th, 2005

Presentations from Spring Intel Developer Forum, including a great deal of talk about multicore processor plans, are available for download from Intel. (Search for “Dual/Multicore” under “Technology Topics.”)

According to ExtremeTech, an Intel exec at the forum said the company “has no less than 15 dual-core development plans underway…Moreover, Intel intends to combine 64-bit processing and dual-core capabilities in its “Extreme Edition” processor family, offering the best of both worlds.”

Cyberinfrastructure for social sciences

Tuesday, June 7th, 2005

In March of this year, the NSF Workshop on Cyberinfrastructure for the Social Sciences was held in Warrenton, VA. The purpose of the workshop was to engage the social science community (sociologists, psychologists, economists, etc. ) and unite them with the computer scientists and engineers to discuss and compose a future plan for Cyberinfrastructure that benefits both research communities in a collaborative way. Two goals were outlined for the workshop and the resulting report:

1. The Workshop Report should lay out a Cyberinfrastructure research, experimentation, and infrastructure path forward for the SBE and CISE community and provide a framework for projects and efforts in this area.

2. The Workshop should provide a venue for community building within the SBE and CISE communities, and in particular a venue for a multi-disciplinary synergistic community which leverages the perspectives and research of both SBE and CISE constituencies.

Both goals were achieved. Many recommendations and challenges resulted from the meeting, which are outlined in the full report (440 K, 50 pages).

Truly useable hi-speed wireless soon?

Monday, June 6th, 2005

When we talk about grid computing, we often talk about bringing computing power to those who need it at a price point they can afford. Nevermind that sharing large data files produced from this computing power still requires wires and often long ones. What if such data sharing could be handled wirelessly? With so much focus on optical networking research, the efforts of the wireless crowd sometimes tend be overlooked. We may be years away from achieving ubiquitous ultra hi-speed, low latency networking using wireless technology, but recent reports make it clear that progress is being made within the mobile telecom/IT industry.

After initial tests in Israel, high speed downlink packet acess (HSDPA), a wireless broadband technology, has just been demonstrated in Japan at the Networld+Interop 2005 in Tokyo. Achieving throughput rates of 14.4 Mbps, which is fast enough for streaming DVD quality video, the demonstration greatly exceeded current commercial-grade wireless capacity. While paltry compared to current wired networks, NASA regularly tests network capabilities, which reveal that

end–to-end file transport from major scientific data repositories to end users laboratories across the shared internet is…typically 50-100 mbps (see the Introduction of the May issue of CTWatch Quarterly)

Technology News Daily has a piece about the Japan demonstration.

FPGA UK

Thursday, June 2nd, 2005

New Scientist reports on an FPGA-based supercomputer being built at the Edinburgh Parallel Computing Centre. The designers say it will operate at one teraflop and will be up to 100 times more energy efficient than a conventional machine of the same power. Scotland’s FPGA High Performance Computing Alliance will “develop software tools to enable programmers to create code for FPGA chips more easily.” FHPCA is led by Nallatech.

(Hat tip to Slashdot.)

For those of you who stumbled here via Google and might not be in the know, an FPGAs are specialized chips that have transistors connected into the most basic functional blocks–logical ands, ors, and multipliers that are used to execute any computer code. Rather than being hard-wired in a predetermined configuration as they are in traditional processors, connections between the functional blocks can be set and reset in FPGAs.

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